1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor (referred to as "IGBT" hereinafter) and, more particularly, it relates to a prevention against latch-up of a parasitic thyristor, a control of change in threshold voltage in controlling the lifetime thereof and an improvement of the trade-off relations between the turn-off time and the ON-state resistance.
2. Description of the Background Art
Generally, an- IGBT device has a plurality of IGBT devices (referred to as "IGBT cell" hereinafter) connected in parallel. FIG. 1 is a sectional view showing a constitution of a conventional n channel IGBT cell, and FIG. 2 is a circuit diagram showing an equivalent circuit thereof.
In FIG. 1, a P.sup.+ collector layer 1 is formed of a P.sup.+ semiconductor substrate. An N.sup.+ epitaxial layer 2A is formed on one of major surfaces of the P.sup.+ collector layer, and an N.sup.- epitaxial layer 2B is formed on the N.sup.+ epitaxial layer 2A. The N.sup.+ epitaxial layer 2A is formed to make the IGBT keep a specific withstand voltage. P-type impurity is selectively diffused in a part of the surface of the N.sup.+ epitaxial layer 2B to form a P well region 3, and N-type impurity of high concentration is selectively diffused in a part of the surface of the P well region 3 to form an N.sup.+ emitter region 4. A gate insulating film 5 is formed on the surface of the P well region 3 between the surface of the N.sup.- epitaxial layer 2B and the surface of the N.sup.+ emitter region 4, and the gate insulating film 5 is also formed on the surface of the N.sup.- epitaxial layer 2B so that it is continuous between adjacent IGBT cells. A gate electrode 6 made of polysilicon, for example, is formed on the gate insulating film 5, and an emitter electrode 7 made of metal such as aluminum is formed electrically connecting to both the P base region 3 and the N.sup.+ emitter region 4. The gate electrode 6 and the emitter electrode 7 make a multi-layered configuration with an insulating film 8 intervening therebetween, so as to electrically connect to all IGBT cells commonly. A collector electrode 9 made of metal is formed on the bottom face of the P.sup.+ collector layer 1 as a single electrode for all the IGBT cells in common.
An area near the surface of the P well region 3 between the N.sup.- epitaxial layer 2B and the N.sup.+ emitter region 4 has a MOS structure of an n channel, and the application of positive voltage to the gate electrode 6 through a gate terminal G causes electrons to flow from the N.sup.+ emitter region 4 to the N.sup.- epitaxial layer 2B and the N.sup.+ epitaxial layer 2A (these epitaxial layers are referred to as "N base layer 2" en bloc hereinafter) through a channel formed near the surface of the P well region 3 just under the gate electrode 6. Symbol I.sub.e shows electron current flowing in this way. On the other hand, holes which are minority carriers are injected from the P.sup.+ collector layer 1 to the N base layer 2. A part of the holes re-combines with the electrons and vanishes, and other part of them flows in the P well region 3 as hole current I.sub.h. As will be recognized, the IGBT works basically as a bipolar transistor and its N epitaxial layer 2B increases in its conductivity due to the effect of conductivity modulation, so that the IGBT, can advantageously implement the lower ON voltage and the larger current capacity compared with those of a conventional power MOS.
However, the IGBT is not without the disadvantage that it can not increase in the operating frequency because the hole current I.sub.h slowly reduces while the IGBT is turned off. Then, an electron beam 40 is irradiated to the IGBT to make crystal defect in the N base layer 2, and thus the lifetime control, where the crystal defect serves as the center of the recombination of holes to increase the operating frequency while the IGBT is turned off, is carried out. At this time, there can be seen the phenomenon that positive fixed electric charge occurs in the insulating film 5 by the passing of the electron beam 40 through the gate insulating film 5 and the threshold voltage V.sub.th is reduced. The extent of the reduction becomes larger as the quantity of irradiation increases. Thus, the device should be designed, estimating in advance the reduction of the threshold voltage V.sub.th caused by the irradiation of electron beam, so that the threshold voltage V.sub.th after the irradiation comes to a desired value.
As can be seen in an equivalent circuit shown in FIG. 2, the IGBT cell has a parasitic PNPN thyristor structure. The parasitic thyristor includes an NPN transistor 10 consisting of the N base layer 2, the P well region 3 and the N.sup.+ emitter region 4 and a PNPN transistor 11 consisting of the P.sup.+ collector layer 1, the N base layer 2 and the P well region 3, and when both of the transistors 10, 11 turn on and the sum of respective current amplification factors .alpha..sub.1, .alpha..sub.2 of the transistors comes to 1, latch-up occurs. Since structurally the thickness of the N base layer serving as a base of the PNP transistor 11 is so thicker than the depth of the diffusion of carriers, the factor .alpha..sub.2 comes to a relatively small value. The NPN transistor 10 is short-circuited between its emitter and base, and thus is difficult to turn on. The parasitic thyristor is not latched up in the ordinary operation, and accordingly, the IGBT cell works as a composite device of an n channel MOSFET 12 and the PNP transistor 11. In this case, since base current in the PNP transistor 11 is controlled by the n channel MOSFET 12, main current I.sub.C flowing from a collector terminal C of the IGBT can be controlled by a control signal applied to a gate terminal G. Assuming that current I.sub.E flows in an emitter terminal E, the following relations are established as follows: EQU I.sub.C =I.sub.E =I.sub.e +I.sub.n ( 1)
However, as the main current I.sub.C increases because of an external cause such as noise applied to the gate terminal G, the electron current I.sub.e and the hole current I.sub.h increase. At this time, if the hole current I.sub.h comes to be beyond a specific value, the NPN transistor 10 becomes conductive due to voltage drop at a resistance R.sub.B in the P well region 3, the current amplification factor a .alpha..sub.1 increases enough to satisfy .alpha..sub.1 +.alpha..sub.2 =1, and the parasitic thyristor comes to be conductive. Thus, the IGBT comes to be latched up. Under the condition, the main current I.sub.C in the IGBT can hardly be controlled by the control signal applied to the gate terminal G, and excessively large main current I.sub.C flows without restriction. To prevent latch-up, impurity concentration in the P well region 3 must be increased to reduce resistance, and the ratio of the hole current I.sub.h flowing just under the N.sup.+ emitter region 4 to an emitter electrode 7 must be diminished.
FIG. 3 is a sectional view showing an example of an IGBT cell structure conventionally employed to prevent latch-up. In this example, the IGBT cell is rectangular in its plane surface, and a P well region 3 of the IGBT cell is formed with a P.sup.+ region 3 in its center by diffusing P-type impurity of the same conductivity type with high concentration. As a result, the resistance of the P well region 3 decreases, and the ratio of the hole current I.sub.h flowing in the center portion of the P well region 3 becomes relatively larger than the ratio of the hole current I.sub.h flowing just under the N.sup.+ emitter region 4, so as to inhibit the NPN transistor 10 from turning conductive.
FIG. 4 is a perspective sectional view showing another example of the IGBT cell structure conventionally employed to prevent latch-up. In this example, a P well region 3 is formed in a stripe, and an N.sup.+ emitter region 4 is formed in a broken stripe pattern where some parts of a stripe are removed. In this way, an area of the P well region 3 between the solid parts of the N.sup.+ emitter region 4 serves as a bypass for the hole current I.sub.h to lower the ratio of the hole current 1.sub.h flowing just under the N.sup.+ emitter region 4. A P.sup.+ region 13 as shown in FIG. 3 is also formed.
If the above-mentioned structure shown in FIG. 3 is employed, especially in an IGBT device of high withstand voltage, the P well region 3 must be deep, and the P.sup.+ region 13 having high impurity concentration must accordingly be formed deeply. However, since the P.sup.+ region 13 is formed by diffusing impurity from the surface, it is unavoidable that the deeper in the P.sup.+ region 13, the lower the impurity concentration becomes, and it is impossible that resistance R.sub.B1 extending in the vertical direction can not sufficiently decrease in resistance value in the deep area. Desirably, the P.sup.+ region 13 is formed extending in the entire area just under the N.sup.+ emitter region 4, but the P.sup.+ region 13 should not reach a channel region just under a gate electrode 6 because it causes the threshold voltage of a MOSFET 12 to change. Taking various errors in the formation into consideration, the P.sup.+ region 13 can not be formed considerably apart from the channel region, and it is impossible that resistance R.sub.B2 extending in the lateral direction can not sufficiently decrease in resistance value in an area near the channel. Thus, there arises the problem that the structure shown in FIG. 3 is unsatisfactory to avoid latch-up.
On the other hand, according to the structure shown in FIG. 4, it is unavoidable that the channel is diminished due to the removal of some parts of the N.sup.+ emitter region 4. The reduction of the channel is disadvantageous to attaining large current capacity. The IGBT cell is a stripe in its plane configuration, and therefore there arises the problem that the densification of the cell arrangement is impeded comparing with an IGBT cell having a rectangular configuration when an IGBT device of large current capacity is manufactured with a lot of IGBT cells connected in parallel.
As shown in FIG. 2, when lifetime control is carried out so as to cause sufficient crystal defect in the N base layer 2 by directing the electron beam 40, the occurrence of the crystal defect necessarily causes the resistance value of the N base layer 2 to increase, and hence the ON resistance of the IGBT increases. In other words, there is trade-off relation between the ON resistance and turn-off time of the IGBT, and there is the problem that the trade-off relation is not optimized in the existing circumstances.
As stated above, since the threshold voltage V.sub.th of the IGBT is reduced by the irradiation of the electron beam 40, the device should be designed, estimating in advance the reduction of the threshold voltage V.sub.th, so that the threshold voltage V.sub.th after the irradiation comes to a desired value, but it requires so much labor.